High speed ADCs are widely used in data processing, in communication systems, in digital oscilloscopes and in other applications. One way to provide for high speed analog to digital conversion in such devices is to use a composite ADC that consists of a number of interleaved sub-ADCs with a common input and sequential timing. In such a case, each sub-ADC generates a partial signal that has a lower data rate than the data rate of the ADC as a whole. All the partial signals are combined into one high speed digital signal that is produced at the output of the composite ADC.
The construction of a high speed ADC comprising a set of interleaved sub-ADCs has a drawback. The signal processing associated with different paths through the various sub-ADCs differs slightly from one sub-ADC to the next. The slight differences occur principally because of variations of the manufacturing processes and the distinctions between hardware components. As a result, each of the partial signals experiences a distinct processing variation and hence, certain aspects of the signals vary across the sub-ADCs.
In particular, each of the partial signals may acquire in the course of conversion, a different DC offset. This mismatch of DC offsets in different sub-ADCs causes specific distortions in the digital signal produced by a composite ADC, the most significant being an appearance of spurious frequency components.
A number of prior art patents propose different ways to eliminate or to reduce DC offsets in composite ADCs, for example, U.S. Pat. No. 7,477,885, U.S. Pat. No. 7,894,561, and U.S. Pat. No. 8,036,622. However, the proposed devices of those patents correct DC offset of a composite ADC as a whole, while mismatch of DC offsets between different sub-ADCs of the respective prior art composite ADCs remains unchanged.
A method and apparatus for compensating mismatch of DC offsets in parallel processing of digital signals is suggested in U.S. Pat. No. 8,294,606. In that patent, it is proposed to process each partial signal that is produced by a sub-ADC of a composite ADC, in a device of a type shown in FIG. 1. The part of the block diagram within dashed line 14 functions as an accumulator. Samples that are applied to an input of the accumulator from block 11, are added in an adder 13 to a value that has been stored in a delay unit 12. A sum that is produced at an output of the adder 13 is loaded into the delay unit 12 as a new accumulated value. In that way, the accumulator 14 compiles a mean value of a sequence of samples that are applied from an output of an adder 10. In adder 10, the accumulated mean value is subtracted from an applied input signal.
The above-described operation of the device in FIG. 1 reduces practically to zero, any DC component in each partial signal of the there-disclosed composite ADC. In that way, the DC offset is removed in each partial signal, eliminating mismatch of DC offsets that existed in the combined signal. However, that proposed procedure for DC offset mismatch compensation of U.S. Pat. No. 8,294,606 has a substantial drawback. Namely, in the frequency domain, the device of the block diagram in FIG. 1 is equivalent to a high pass filter. As a consequence, relatively low frequency components of an input signal are subject to relatively high attenuation compared to attenuation of relatively high frequency components, while a DC component of the input signal does not pass through the proposed device at all. Because of that blocking of DC components, the procedure for DC offset mismatch compensation of U.S. Pat. No. 8,294,606 is problematic for applications of composite ADCs where the DC component of the processed signal carries essential information, as is the case in digital measuring instruments, such as digital oscilloscopes and other similar devices. The method of U.S. Pat. No. 8,294,606 cannot be used in such applications, as well as in applications, where the frequency distortions of processed signal are intolerable
The present technology provides a device that removes DC offset mismatches in a composite ADC, while passing the DC component, without distortions of processed signal properties.